In Systematic Design of Analog CMOS Circuits (Jespsers, Murmann) page 343, the following is stated in the context of where to place the non-dominant pole in a second-order loop transfer function of a switched-capacitor amplifier:
The case of ωp2/ωu1 = 4 (Q = 0.5) results in a critically damped step response. This corresponds to the fastest possible settling without overshoot [7] and is the preferred choice for SC [switched capacitor] circuits that are designed for maximum speed. Designing for ωp2/ωu1 < 4 is not recommended to avoid overshoot, which is difficult to manage if the goal is to create a robust design.
The emphasis is mine, and also see the figure below if helpful. Note that the reference [7] in the quote is this paper. (I don't think this paper addresses my question, below).
My questions are:
- Why is overshoot "difficult to manage" in a "robust" design?
- What are the main problems that overshoot could cause? The above quote comes from the context of switched-capacitor circuits, so that may be relevant. The main thing I can think of is maybe the overshoot could result in dropping the output stage devices / input devices of the next stage out of saturation if the overshoot makes the signal swing too big, I'm unsure if this is one such problem / if there are others.
